1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell array in which plural nonvolatile memory cells are arranged in a row direction and a column direction, respectively, and plural word lines and plural bit lines are arranged in the row direction and the column direction, respectively, in order to select a predetermined memory cell or a memory cell group from the plural memory cells. More particularly, the present invention relates to a nonvolatile semiconductor memory device in which each memory cell includes a variable resistance element for storing information by change in electric resistance, thus allowing data to be electrically written and reset (erased).
2. Description of the Related Art
Examples of a nonvolatile semiconductor memory device capable of electrically writing and resetting (erasing) data with the use of a variable resistance element include an MRAM (Magnetic Random Access Memory) and an RRAM (Resistance control nonvolatile RAM) which will be described later.
In the MRAM, an MRAM memory element including a variable resistance element has a ferromagnetic layer where the resistance is determined by magnetization in a direction. The resistance in the memory element is small when the magnetization across the ferromagnetic layer is in parallel. On the other hand, the resistance in the memory element is large when the magnetization across the ferromagnetic layer is not in parallel. The layer construction of the MRAM memory element is formed by a GMR (Giant MagnetoResistive) memory, a TMR (Tunneling MagnetoResistive) memory, and a CMR (Colossal MagnetoResistive) memory.
The GMR memory element has at least two ferromagnetic layers and a non-magnetic conductor layer interposed therebetween. As the GMR memory element is based on whether the magnetization across the two ferromagnetic layers is in parallel or not, its GMR effect can be sustained.
TMR memory element has at least two ferromagnetic layers and an insulating non-magnetic layer interposed therebetween. The insulating non-magnetic layer is arranged to flow a tunneling current between the two ferromagnetic layers. The ferromagnetic layers produce a magnetoresistive effect due to a spin polarization tunneling current running through the insulating non-magnetic layer between the two ferromagnetic layers. The electric resistance in the TMR memory element depends on whether the magnetization across the ferromagnetic layers is in parallel or not.
The CMR memory element employs a thin film material having a perovskite (La(Sr)MnO) structure which provides a CMR effect greater in resistance change than a GMR effect.
It is said that the RRAM is a type of MRAM because its RRAM memory element as a variable resistance element provides a magnetoresistive effect. The variable resistance element in the RRAM has a PrCaMnO-based CMR layer of which the magnetoresistive effect is different in the principles from that of a TMR layer in the MRAM.
FIG. 14 illustrates a section of a conventional MRAM memory cell array where a TMR memory element is implemented with the use of a spin injection method. In the figure, two memory cells are shown for simplicity. Actually, the memory cells are arranged in rows and columns and connected with signal lines including, for example, word lines WL, bit lines BL, and common source lines SL, as shown in FIGS. 16 and 17. In this case, the MRAM memory is implemented with a P-substrate (P-well), where a first BL is operatively coupled to the P-substrate via a first TMR memory element and a first N+ diffusion region on the left hand side, and a second BL is operatively coupled to the P-substrate via a second TMR memory element and a second N+ diffusion region on the right hand side. In addition, the SL is operatively coupled to the P-substrate through a third N+ diffusion region in the middle. The spin injection method allows the magnetization to be inverted directly by a current supplied to the TMR memory element. When the current supplied to the TMR memory element is reversed (in the feed/draw direction), the magnetization in the free layer shifts to in parallel or not in parallel with the magnetization of the fixed layer. The spin feed method is so called because the magnetization is inverted by the action of spin polarized electrons in the current (See “Nikkei Electronics” 1–20 in 2003, No. 839, pp. 98–105).
FIG. 15 illustrates a section of a conventional RRAM memory cell array where a CMR memory element is implemented with the use of a voltage pulse applying method. In the figure, two memory cells are shown for simplicity. Actually, the memory cells are arranged in rows and columns and connected with signal lines including, for example, word lines WL, bit lines BL, and common source lines SL, as shown in FIGS. 16 and 17. Similarly, the RRAM memory is implemented with a P-substrate (P-well), where a first BL is operatively coupled to the P-substrate via a first TMR memory element and a first N+ diffusion region on the left hand side, and a second BL is operatively coupled to the P-substrate via a second TMR memory element and a second N+ diffusion region on the right hand side. In addition, the SL is operatively coupled to the P-substrate through a third N+ diffusion region in the middle. The magneto-resistive effect of the CMR memory element is different in the principles from that of a TMR layer used in common MRAM.
The storage of data can be implemented by the fact that when the CMR memory element in RRAM is loaded with a pulsed voltage, its resistance changes. The CMR layer is made of, e.g., PCMO (Pr0.7Ca0.3MnO3). The relationship between supplied voltage and resistance is specifically disclosed in “Novel colossal magneto-resistive thin film nonvolatile resistance random access memory”, IEDM, 2002, pp. 193–196. The materials for RRAM memory are depicted in U.S. Pat. No. 6,473,332.
The CMR memory element in RRAM is as simple as having a CMR layer disposed between the upper electrode (Pt) and the lower electrode (Pt). As shown in FIGS. 14 and 15, the RRAM memory cell with the voltage pulse applying method and the MRAM memory cell with the spin injection method are equally expressed by an equivalent circuit. The conventional memory cell array shown in FIGS. 14 and 15 has a single memory cell of either MRAM or RRAM implemented by a series circuit of a memory element 1 and a selection transistor 2 where the memory element 1 is directly connected at one end to a bit line BL.
As best shown in FIG. 16, the reset operation (for deleting data) of RRAM is carried out with the supply of voltages, 7 V to the selected word line WLs, 0 V to the non-selected word line WLu, and 0 V to the selected bit line BLs, while the common source line SL is loaded with a pulsed voltage which has a pulse width of substantially 1000 ns and is shifted from 0 V to 5 V and then to 0 V. After the reset operation, the resistance of RRAM memory element becomes low (about 4 kΩ, see FIG. 18). The low resistance represents a storage of data “1”. As shown in FIG. 17, the write operation of RRAM is carried out with the supply of voltages, 7 V to the selected word line WLs, 0 V to the non-selected word line WLu, and 0 V to the common source line SL, while the selected bit line BLs is loaded with the pulsed voltage which has a pulse width of substantially 1000 ns and is shifted from 0 V to 5 V and then to 0 V. After the write operation, the resistance of RRAM memory element becomes high (about 140 kΩ, see FIG. 18). The high resistance represents a storage of data “0”. If the width of a pulse supplied to the RRAM memory element is increased (for example, to 2000 ns or longer), the resistance will be declined. The relationship between applied voltage and resistance in RRAM memory is disclosed in “Nikkei Electronics”, 1–20 in 2003, No. 839, p. 105.
MRAM with the spin injection method is differentiated from RRAM by the fact that a pulsed current is used instead of a pulsed voltage. When the pulsed current but not the pulsed voltage is reversed (in the feed/draw direction), the magnetization in the free layer is shifted to in parallel or not in parallel to the magnetization of the fixed layer, thus switching the resistance of the MRAM memory element from high to low or vice versa. Both the RRAM memory element with the pulsed voltage application method and the MRAM memory element with the spin injection method are as small in the size as DRAM and also compatible with a multi-bit system, hence decreasing the cost per storage size.
Also, conventional MRAM and RRAM memories permits each memory element to be connected directly to the bit lines. It is however true that the memory element (at TMR or CMR layer) is adversely affected when the potential at the bit line is fluctuated by the effect of system noise or any other fault abruptly generated during the startup or energization. When the bit line is loaded with a pulsed voltage or a potential for conducting a current, the memory element in a non-selected memory cell receives the voltage or potential. The voltage and current received by the bit line may affect the resistance and if worse, interrupt the data stored in the memory element of the non-selected memory cell.
More particularly, when the bit line is loaded with 0 V at the standby mode, its potential is 0 V as well as the N+ diffusion potential under the TMR layer shown in FIG. 14. Then, when the bit line receives a current for reading or writing of data, the not selected TMR layer connected directly with the bit line is also affected by charging and discharging currents running in the direction of N+ diffusion across the memory element. As the charging and discharging currents run several times through the TMR layer in the non-selected memory cell, they may interrupt the data stored in the MRAM, which stores the data “0” or “1” by the current direction, hence declining the reliability of data storage.
Similarly, when the bit line is loaded with 0 V at the standby mode in RRAM, its potential is 0 V as well as the N+ diffusion potential under the CMR layer shown in FIG. 15. Then, when the bit line receives a pulsed voltage for reading or writing of data, the not selected CMR layer connected directly with the bit line is also affected by charging and discharging currents running transiently in the direction of N+ diffusion across the memory element. This causes a potential (voltage) between both ends of the CMR layer. As the charging and discharging currents run several times through the CMR layer in the non-selected memory cell, they may interrupt the data stored in the RRAM, which stores the data “0” or “1” by the voltage application direction, hence declining the reliability of data storage.
In addition, when the length of a pulse to be applied is increased (for example, to 2000 ns or longer), the resistance of the RRAM memory increases to a maximum and then decreases. It is therefore necessary for compensation to carefully control the pulsed voltage.
Moreover, the resistance of the RRAM memory element is turned to low (4 kΩ) as the reset operation has been completed. This causes the memory cell to receive a large amount of current depending on the behavior of the reset operation. When the reset operation is carried out on the basis of bytes, the memory element in the non-selected memory cell connected to the non-selected bit line at the floating state receives a transient charging or discharging current like that at the write operation and may suffer from an abundance of voltage/current.
When the resistance of its memory element is declined too low after the reset operation, the memory cell needs to receive a greater level of current during the write operation. It is hence necessary to increase the ability of a driver circuit for supplying the memory cell with a pulsed voltage/current at the write operation. A large size of the driver circuit will thus be provided. For storage of data, a group of the memory cells to be written are held at the low resistance state (about 4 kΩ, see FIG. 18). Since the common source line receives a sum of input currents to the memory cells of the group at the start of the write operation, its size in the cross section has to be increased. As the write operation proceeds, the resistance of each memory element is increased from its low level. It may hence be troublesome to determine the width of a pulse in the pulsed voltage at the write operation.
Furthermore, the reset operation for a group of memory cells is hardly uniform. It is true that the memory elements in the memory cells of a group to be reset are not identical in the resistance but range from higher to lower at inconsistency. Even when the reset operation is triggered under the same conditions, the memory elements may be varied more or less in the resistance.